Building Boreal FPGA Bit Files

The build workflow of Boreal is very well streamlined and consists of two main steps:

1. Creating a Vivado project for a device and board targets
2. Building a bitfile for a device and board targets

This section provides a step-by-step guide to the build workflow using the Boreal Manager. The workflow’s final output is a bitstream and hardware description file tailored to a specific device and board combination.

1. Creating the Vivado project for a device and board targets link

  ./boreal-manager.py create --device <device-name> --board <board-name>
  

This step creates the Vivado project of the target device and board.

2. Building a bit file for a device and board targets link

  ./boreal-manager.py build --device <device-name> --board <board-name>
  

This step initiates the synthesis, implementation, and bitstream (*.bit) generation for the specified device and board. Additionally, it produces a hardware description file (*.xsa). The *.bit and *.xsa files can be found inside the implementation output folder at <path-to-project/<project-name>.runs/impl_1.