peary/interfaces/AXI4Lite/axi4lite.hpp

Peary AXI4Lite Interface. More…

Namespaces

Name
peary
peary::interface

Classes

Name
struct peary::interface::AXI4LiteInterface
class peary::interface::AXI4LiteEndpoint Peary AXI4Lite Interface Endpoint.

Detailed Description

Peary AXI4Lite Interface.

Copyright: Copyright (c) 2016-2025 CERN and the Peary Caribou authors. This software is distributed under the terms of the LGPL-3.0-only License, copied verbatim in the file “LICENSE.md”. SPDX-License-Identifier: LGPL-3.0-only

Source code 

  
#pragma once

#include <cstdint>
#include <cstdio>
#include <string>
#include <vector>

#include <fcntl.h>
#include <sys/mman.h>

#include "peary/interfaces/Endpoint.hpp"
#include "peary/interfaces/exceptions.hpp"
#include "peary/utils/datatypes.hpp"

namespace peary::interface {

    struct AXI4LiteInterface {};

    class AXI4LiteEndpoint : public Endpoint<AXI4LiteInterface, size_t, uintptr_t> {
    public:
        AXI4LiteEndpoint(std::string const& devpath, const utils::memory_map& mem);
        ~AXI4LiteEndpoint();

    protected:
        pair_t write_impl(const pair_t&) override;

        vector_t read_impl(const reg_t&, const unsigned int) override;

        uintptr_t read_word(const reg_t& offset) const;

    private:
        // Access to FPGA memory mapped registers
        int _memfd;

        // Buffer
        void* _mem_buf;

        // Memory map
        const utils::memory_map _mem_map;
    };

} // namespace peary::interface

Updated on 2026-01-30 at 22:01:05 +0100