peary::interface::SPIBusEndpoint
peary::interface::SPIBusEndpoint
SPI bus interface class. More…
#include <peary/interfaces/SPI_BUS/spi_bus.hpp>
Inherits from peary::interface::SPIEndpoint<>, peary::interface::Endpoint< SpiInterface, uint8_t, uint8_t >
Public Functions
| Name | |
|---|---|
| SPIBusEndpoint(std::string const & bus, const reg_t address_bits, const data_t data_bits, const bool ws, const bool align_msb)Constructor for SPIBusEndpoint. | |
| ~SPIBusEndpoint() =default | |
| pair_t | write_impl(const pair_t & data) overrideWrite data to a register. |
| std::vector< pair_t > | write_impl(const std::vector< pair_t > & data) overrideWrite multiple data to registers. |
| vector_t | read_impl(const reg_t & reg, const unsigned int length) overrideRead multiple data from a register. |
Additional inherited members
Public Types inherited from peary::interface::SPIEndpoint<>
| Name | |
|---|---|
| using typename Base::reg_t | reg_t |
| using typename Base::pair_t | pair_t |
| using typename Base::data_t | data_t |
| using typename Base::vector_t | vector_t |
Public Functions inherited from peary::interface::SPIEndpoint<>
| Name | |
|---|---|
| SPIEndpoint(const std::string & bus)Constructor for SPIEndpoint. | |
| ~SPIEndpoint()Destructor for SPIEndpoint. |
Protected Attributes inherited from peary::interface::SPIEndpoint<>
| Name | |
|---|---|
| int | fd_ |
| const uint32_t | bits_per_word |
Public Types inherited from peary::interface::Endpoint< SpiInterface, uint8_t, uint8_t >
| Name | |
|---|---|
| using RegisterType | reg_t |
| using DataType | data_t |
| using std::pair< RegisterType, DataType > | pair_t |
| using std::vector< DataType > | vector_t |
Public Functions inherited from peary::interface::Endpoint< SpiInterface, uint8_t, uint8_t >
| Name | |
|---|---|
| Endpoint(const Endpoint & ) =delete | |
| Endpoint & | operator=(const Endpoint & ) =delete |
| Endpoint(Endpoint && ) =delete | |
| Endpoint & | operator=(Endpoint && ) =delete |
| std::string | info() constReturn human-readable endpoint information. |
| data_t | write(const data_t & value)Write a single data word to a device which does not contain internal registers. |
| vector_t | write(const vector_t & values)Write multiple data words to a device which does not contain internal registers. |
| pair_t | write(const pair_t & regData)Write a single data word to a device containing internal registers. |
| vector_t | write(const reg_t & reg, const vector_t & values)Write multiple data words to a specific register of a device containing internal registers. |
| std::vector< pair_t > | write(const std::vector< pair_t > & regDataVec)Write multiple data words to multiple registers of a device containing internal registers. |
| data_t | read()Read a single data word from a device which does not contain internal registers. |
| vector_t | read(unsigned int count)Read multiple data words from a device which does not contain internal registers. |
| vector_t | read(const reg_t & reg, unsigned int count)Read a single data word from a specific register of a device containing internal registers. |
Protected Functions inherited from peary::interface::Endpoint< SpiInterface, uint8_t, uint8_t >
| Name | |
|---|---|
| Endpoint(const std::string & info) | |
| virtual | ~Endpoint() =default |
Detailed Description
class peary::interface::SPIBusEndpoint;
SPI bus interface class.
In this implementation 2 type of the SPI frames are considered: read and write frame. The type of the frame is distinguished by the most significant bit of the SPI transaction on MOSI lines. The polarity of this bit is distinguished by write strobe (ws) parameter of the class constructor. The frame type bit in the SPI frame is followed then by address of the register to be accessed and data. The maximum width of SPI frame supported by the class is limited by the width of uintmax_t type.
E.g. addressBits = 8, dataBits = 8, ws = 1
Read operation:
1b 8bit 8bit
MOSI | !ws | ADDR | - | MISO | - | - | DATA |
Write operation:
1b 8bit 8bit
MOSI | ws | ADDR | DATA | MISO | - | - | - |
As most of the SPI drivers support properly on 8 bits_per_word size, the actual SPI transaction has length which is multiple of 8-bits. alignMSB defines whether the read/write operation is aligned to MSB or LSB. for the previous example, alignMSB=1 would correspond to the actual SPI transaction:
Read/write operation: 1b 8bit 8bit 7bit MOSI | ws | ADDR | (DATA) | PADDING MISO | - | - | (DATA) | PADDING
While alignMSB=0 would produce:
Read/write operation: 7b 1b 8bit 8bit MOSI PADDING | ws | ADDR | (DATA) | MISO PADDING | - | - | (DATA) |
Public Functions Documentation
function SPIBusEndpoint
explicit SPIBusEndpoint(
std::string const & bus,
const reg_t address_bits,
const data_t data_bits,
const bool ws,
const bool align_msb
)
Constructor for SPIBusEndpoint.
Parameters:
- bus The device path for the SPI bus interface
- address_bits The number of bits used for the register address (max 63)
- data_bits The number of bits used for the data (max 63)
- ws The write strobe polarity (true for active high, false for active low)
- align_msb If true, the SPI frame is aligned to MSB, otherwise to LSB
function ~SPIBusEndpoint
~SPIBusEndpoint() =default
function write_impl
pair_t write_impl(
const pair_t & data
) override
Write data to a register.
Parameters:
- data A pair containing the register address and the data to be written
Return: A pair containing the register address and the data read back from the device
function write_impl
std::vector< pair_t > write_impl(
const std::vector< pair_t > & data
) override
Write multiple data to registers.
Parameters:
- data A vector of pairs containing the register addresses and the data to be written
Return: A vector of pairs containing the register addresses and the data read back from the device
function read_impl
vector_t read_impl(
const reg_t & reg,
const unsigned int length
) override
Read multiple data from a register.
Parameters:
- reg The register address to read from
- length The number of data items to read
Return: A vector containing the data read from the device
Updated on 2026-01-30 at 22:01:05 +0100